“As China begins to deploy third-generation (3G) wireless services in densely populated cities, various objective limitations drive users to put forward more important demands for high-performance analog-to-digital converters (ADC). High-speed ADC applications are diverse, but low power consumption is a key factor commonly required by users. To provide users with competitive advantages for their final products, ADCs need to achieve high resolution, high speed, and high performance ON the basis of lower power and smaller size.
Author: ToddNelson AtshushiKlwll
As China begins to deploy third-generation (3G) wireless services in densely populated cities, various objective limitations drive users to put forward more important demands for high-performance analog-to-digital converters (ADC). High-speed ADC applications are diverse, but low power consumption is a key factor commonly required by users. To provide users with competitive advantages for their final products, ADCs need to achieve high resolution, high speed, and high performance on the basis of lower power and smaller size.
3G infrastructure requirements
High-speed ADCs play an important role in the receive (Rx) and transmit (Tx) paths of GSM, WCDMA, and TD-SCDMA base stations. Although the previous generation of designs widely used high-power ADCs that consume more than 1500mW, new base station designs still require high-performance low-power ADCs. This is especially true in metropolitan areas, because metropolitan areas require dense networks of micro base stations and pico base stations to ensure service quality. In addition to the obvious requirement for low-power operation, small-sized base stations have additional restrictions on the heat dissipation of core components. Limited system heat dissipation capacity often becomes a bottleneck in achieving integration density. Competitive system design schemes require ADCs to achieve high performance on the basis of compactness and low power, while maintaining low temperatures.
Due to the different requirements of end customers, the Rx channel architectures chosen by different manufacturers are also very different. Previous generation receivers usually used dual ADCs to sample the I and Q signals demodulated from a single channel.Because here
In this method, the I and Q signals are relatively close to the baseband, and the performance requirements for the dual ADC are relatively low. As far as next-generation designs are concerned, the trend is to support multi-channel transmission by a single Rx channel by directly sampling at the intermediate frequency (IF). This architecture has higher requirements for ADC. Taking into account the frequency planning of multiple carriers, 14 bits usually require a sampling rate of 65Msps or 80Msps. Since the IF frequency is often between 70MHz and 140MHz, good under-sampling performance is also necessary.
A high-performance ADC is also required in the Tx path of a 3G base station. In the Tx path, the non-linearity of the output power Amplifier (PA) limits the system-level performance, so different methods are used to linearize the PA output. Previously, PA linearization was achieved through full analog technology such as the feedforward method. As far as next-generation designs are concerned, the development trend is to compensate for its non-linearity by digitally pre-distorting the PA input using a fast feedback path.
For example, although mainstream WCDMA base stations generally require a sampling rate of 125Msps at 12 bits, the sampling rate required for PA linearization depends on the number of digitized carriers and the frequency range in which the linearization is effective. In order to reduce the RF downconversion order, the current trend is to sample at a higher IF frequency. Since the target IF frequency is common in the range of 100MHz to 200MHz, the ADC must have excellent under-sampling performance.
When digitizing multiple WCDMA modulated carriers at the same time, an important metric for this application is the adjacent channel leakage rate (ACLR) of the ADC. Figure 1 shows the FFT spectrum of a common scheme, in which 4 WCDMA carriers centered at 140MHz are sampled at 122.88Msps sampling rate and 12-bit resolution. The ACLR measurement results reflect the frequency signal-to-noise ratio (SNR) of the ADC near the edge of each carrier and its intermodulation distortion. This measurement is often regarded as a key test to determine whether a particular ADC can be used for a given PA linearization application.
How to choose a high-speed ADC
The performance characteristics of high-speed ADCs have a huge impact on the design of the entire signal processing chain. While considering the impact of ADC on baseband, system designers must also consider the impact on radio frequency (RF) and digital circuit systems. Since the ADC is located between the analog and digital areas, the responsibility for evaluation and selection often falls on the system designer, and the system designer is not all ADC experts.
In addition to the user needs mentioned above, there are some important factors that users often overlook when initially choosing a high-performance ADC. They may have to wait until the initial design prototype is about to be completed to know all the system-level results, and at this time it is unlikely to choose another ADC.
One of the important factors affecting many wireless communication systems is the degree of distortion at low input signal levels. The signal level that most wireless transmissions reach the ADC is much lower than the full-scale input range. In order to ensure that the power of the multiplexed signal is not compressed when it is converged to the ADC input at the same time, the front-end gain of the signal chain is designed to be slightly lower than the full-scale range of the ADC. However, almost all high-speed ADCs guarantee their SFDR performance at the input level from -1dB of full scale. In addition, most data sheets have typical SFDR graphs over a wide input amplitude range. The user should carefully observe the curve to verify whether the operation is stable and predictable. The presence of any large step or sawtooth characteristics at low input amplitudes indicates system nonlinearity in the ADC transfer function. Since the linearity of the transfer function is closely related to low input level distortion, ADCs with strict guarantees for maximum integral nonlinearity (INL) generally have more stable distortion performance at low input amplitudes.
It is very important to select an ADC that has guaranteed minimum or maximum limits for all key performance specifications such as INL, differential non-linearity (DNL), SNR, and SFDR. These specifications should be guaranteed over the entire operating temperature range of the application. Users especially need to pay attention to whether these key parameters can only be guaranteed in a small temperature range or at room temperature. If the precision operational amplifiers and fast comparators inside high-speed ADCs are not robust enough, they may change greatly when the temperature changes. Choosing an ADC that does not have a guaranteed limit within a wide temperature range will bring unnecessary risks to the design.
The size requirement of the solution is also critical, because the PCB area of the urban base station design is very limited. Since the use of small flat IC packages such as QFNs reduces the area of the ADC itself, the overall solution area may actually be much larger. A closer look at the recommended circuit will reveal that many high-speed ADCs require a large number of Capacitors with a large capacitance (such as 10μF). These capacitors take up much larger PCB area than the ADC. Due to the parasitic inductance of the package connection lines, many high-speed ADCs require such large external capacitors to bypass the power supply and internal reference circuitry. To achieve a small size in the final product, the ADC is required not only to adopt a small package, but also to minimize the size and number of these large external bypass capacitors.
In addition to novel circuit design techniques, technological progress is also important in the development of low-power high-speed ADCs. It is particularly worth mentioning that, due to the initial drive of digital technology, the continuous adjustment of silicon technology processes, ADCs manufactured using CMOS technology have also benefited a lot.
As far as analog circuit design is concerned, the key advantage of CMOS process adjustment lies in lower power and higher speed operation. Unlike traditional digital CMOS circuits that only consume dynamic power, most of the power consumed by ADCs is caused by quiescent current used to bias analog circuits such as amplifiers and comparators. For a given analog bias current, a shorter channel length (L) process provides a higher transconductance (gm) for the Transistor, which is a key measure of device performance. The smaller Transistor size also makes the parasitic capacitance of the device smaller. At each pipeline stage of a high-speed ADC, the analog stabilization speed of critical circuits such as precision operational amplifiers is largely determined by the Transistor gm. Therefore, in the case of a given total bias current, shortening L will make the work faster.
Another benefit is that the supply voltage usually decreases as L decreases, so even if the analog bias current remains the same, the overall power consumption will decrease. By adjusting the fineness of the craft, the ADC designer can flexibly increase the speed at a given power level or reduce the power at a given speed.
However, there is a serious shortcoming in the process adjustment of analog circuits. Due to the reduced power supply Voltage, the full-scale input range of the ADC must also be reduced in order to provide sufficient voltage space for analog circuit systems such as operational amplifiers. A smaller input range results in lower signal power, and SNR will decrease with process adjustments. The challenge of low-power, high-performance design solutions is also to reduce the noise generated by the ADC to maintain a sufficient signal-to-noise ratio.
Introduction of Linear Technology’s Low-Power High-Performance ADC
Obviously, low power and high performance are the main requirements of users in the market. To meet market demand, Linear Technology has recently introduced several high-speed ADC series.
LTC2224/2222/2223 are pin-compatible 3.3V 12-bit 135/105/80Msps ADCs, optimized for under-sampling. The LTC2224 series has an SNR of more than 67.5dB and an SFDR of 80dB when the input frequency is up to 140MHz, while only consuming 630mW of power at 135Msps. The highly optimized track and hold design continuously maintains an SNR of more than 65dB and an SFDR of 75dB for input frequencies up to 400MHz, and has excellent under-sampling performance at low power. Figure 2 summarizes the high-frequency performance of the LTC2224. Even those devices that consume much higher power rarely have such under-sampling performance at high input frequencies. As shown in Figure 3, as far as 12-bit ADC is concerned, the linearity of the ADC transfer function is also very high, which is comparable to many 14-bit devices. As expected by the clean transfer function, the distortion performance at small input amplitudes is also quite stable. The LTC2224 series is very suitable for WCDMA PA linearization applications that require low power and excellent under-sampling performance.
The LTC2249/LTC2229 series are pin-compatible 3V 14-bit/12-bit ADCs with speeds up to 80Msps. Table 1 summarizes the performance characteristics of these devices. These high-speed ADCs have extremely low power, ranging from 222mW at 80Msps for LTC2249/LTC2229 to 60mW at 10Msps for LTC2245/LTC2225. Achieving these low powers does not lose performance. For example, as shown in Figure 4, the LTC2248 (65Msps) maintains 74dB SNR and 80dB SFDR for inputs far away from the Nyquist Frequency. By using a 5mm×5mm tiny QFN package, these two series have also achieved a small size. Most of the necessary bypass capacitors are directly integrated on the chip, so these devices require only a small amount of low-value external bypass ceramic capacitors to achieve the performance shown in the data sheet. The pin-compatible LTC2249 and LTC2229 series have the characteristics of high performance, low power consumption and small size. Make them very suitable for small WCDMA, GSM and TD-SCDMA base stations.
The urban base station design scheme requires good SNR and SFDR performance at high input frequency and wide input bandwidth. This requires a high linearity track and hold design and small internal sampling clock jitter; each aspect requires power consumption in the ADC. The SNR and SFDR of many low-power ADCs decrease rapidly as the input frequency increases, because the internal clock jitter and the non-linearity of the track and hold circuit mainly affect the response. However, the recently introduced low-power and small-size high-performance ADCs overcome these problems and meet the needs of the new generation of wireless communications market for smaller, more power-efficient products.