The Design of Interface Communication System Based on SX52BD Single-chip Microcomputer

The extended capability port mode ECP (Extented Capability Port) is one of the working modes of the IEEE 1284 standard. It can realize two-way data transmission, with functions such as DMA transmission, data RLE compression, and two-way addressing. It requires that the hardware ON both sides of the host peripheral must implement the function of a state machine, that is, automatically generate various control signals. ECP mode is the only IEEE 1284 transmission protocol that defines register implementation.

Author: Yi Wei Wei

introduction

The extended capability port mode ECP (Extented Capability Port) is one of the working modes of the IEEE 1284 standard. It can realize two-way data transmission, with functions such as DMA transmission, data RLE compression, and two-way addressing. It requires that the hardware on both sides of the host peripheral must implement the function of a state machine, that is, automatically generate various control signals. ECP mode is the only IEEE 1284 transmission protocol that defines register implementation. When operating the ECP parallel protocol on the computer side, only reading and writing the corresponding registers will trigger the hardware to complete various timings. The data transfer rate of ECP mode can reach 2~4MB/s.

SX52BD is a SX series product, which is a configurable communication controller manufactured using CMOS technology. It is a high-speed single-chip microcomputer, the instructions are mostly single-cycle, and its operating frequency can reach 50MHz. Due to its unique speed, the device can realize virtual peripherals (the function of software instead of hardware). The communication described in this article is based on this.

1 ECP protocol

ECP transmission is realized through a standard parallel port. The pin definition of its DB25 interface is as follows:

1―HostClk; 2~9―Bidirectional D1~D8;
10―PeriphClk; 11―PeriphAck;
12―nAckReverse; 13―Xflag;
14―HostAck; 15―nPeriphRequest;
16―nReverseRequest; 17―IEEE1284Active;
18~25—Each signal ground.

The ECP mode is divided into the following 8 operating stages.

The Design of Interface Communication System Based on SX52BD Single-chip Microcomputer

① Mode negotiation stage. The host puts the ECP capability request value on the data bus, and then sets IEEE 1284 Active to high and HostAck to low. The peripheral should set PeriphClk to low, nPeriphRequest to high, Xflag to high, and nAckReverse to high. The host sets HostClk to low, and then sets HostClk and HostAck to high, indicating that a peripheral compatible with ECP mode has been confirmed. Then, externally set nAckReverse to low, PeriphAck to low, Xflag to high, and PeriphClk to high. The interface enters the setup phase.

② ECP setting stage. The host sets HostAck to low, and externally sets nAckReverse to high to respond to the host. The interface enters the forward idle phase and can start to transmit data.

③Forward idle phase. Externally set PeriphAck to low, the host can start to transmit data when detecting this signal.

④ ECP forward transmission stage. The host puts the data on the data bus and sets HostClk to low. Externally set PeriphAck to high and answer. The host sets HostClk to high, and the peripheral receives data and sets PeriphAck to low to complete the transmission.

This kind of handshake is called interlocked handshake. Interlocking handshake means that each control signal transition is answered by the other party of the interface. In this way, the peripheral can control the transmission time to meet the needs of its operation.

⑤ ECP forward to reverse conversion stage. In the positive idle phase, the host sets the 8-bit data bus to a high impedance state and sets HostAck to low. To wait for the minimum setup time, set nReverseRequest to low. Externally set nAckReverse to low response and enter the reactive idle phase.

The Design of Interface Communication System Based on SX52BD Single-chip Microcomputer

2 Introduction to SX52BD MCU

SX52BD’s on-chip program memory capacity is 4096 bytes, and the data memory capacity is 262×8 bits. SX52BD has 5 8-bit I/O ports A, B, C, D, E, 2 16-bit timers with 8-bit prescaler, 1 universal 8-bit timer with prescaler, and 1 analog comparison Detector, a brownout detector and watchdog timer, an internal RC oscillator. Ports A, B, and C are two-way I/O ports; port B can be used as input for configuration, comparator, and timer 1; port C can be used as input for timer 2; ports D and E are only used for input.

SX52BD has 3 different addressing modes: indirect addressing, direct addressing, and semi-direct addressing. The choice of register addressing mode depends on the value of the 5-bit “fr” in the instruction.

*Indirect mode: fr=00h
*Direct mode: (fr bit 4=0) fr=01h~0Fh
*Semi-direct mode: (fr bit 4=1) fr=10h~1Fh

Since the SX52BD runs at a speed of up to 50MHz, the timing generated by the command operation can fully meet the timing requirements of the ECP protocol, and its I/O port drive capability meets the requirements of the PC. Therefore, there is no need to use any additional hardware circuits to generate timing. This is the concept of virtual peripherals.

3 The realization of ECP communication between SX52BD and PC

Due to the use of virtual peripherals, the hardware circuit structure is extremely simple: just connect the 25 bidirectional I/O ports of the SX52BD single-chip microcomputer to the PC.

The realization of ECP communication is completed by software. After the host has set up the BIOS, it can directly generate the timing required by the hardware through the operation register. The register definition is shown in Table 1.

Table 1 Register definition (base address 0x378)
The Design of Interface Communication System Based on SX52BD Single-chip Microcomputer

The bit definition of the status register dsr is shown in Figure 1, and the bit definition of the control register dcr is shown in Figure 2. The use of ECP to FIFO and DMA is defined in the extended control register ecr, and it is operated only when the speed is high.

The simple ECP protocol is listed below. Figure 3 is the program flow chart on the SX52BD side, and Figure 4 is the program flow chart on the PC side.

Concluding remarks

Generally speaking, because the ECP protocol has perfect functions and simple implementation, it is not very strict on time requirements, and has high application value in many occasions where transmission rate requirements are not particularly high. In addition, the virtual peripherals of the SX series microcontrollers have a wide range of applications.

Author: Yi Wei Wei

introduction

The extended capability port mode ECP (Extented Capability Port) is one of the working modes of the IEEE 1284 standard. It can realize two-way data transmission, with functions such as DMA transmission, data RLE compression, and two-way addressing. It requires that the hardware on both sides of the host peripheral must implement the function of a state machine, that is, automatically generate various control signals. ECP mode is the only IEEE 1284 transmission protocol that defines register implementation. When operating the ECP parallel protocol on the computer side, only reading and writing the corresponding registers will trigger the hardware to complete various timings. The data transfer rate of ECP mode can reach 2~4MB/s.

SX52BD is a SX series product, which is a configurable communication controller manufactured using CMOS technology. It is a high-speed single-chip microcomputer, the instructions are mostly single-cycle, and its operating frequency can reach 50MHz. Due to its unique speed, the device can realize virtual peripherals (the function of software instead of hardware). The communication described in this article is based on this.

1 ECP protocol

ECP transmission is realized through a standard parallel port. The pin definition of its DB25 interface is as follows:

1―HostClk; 2~9―Bidirectional D1~D8;
10―PeriphClk; 11―PeriphAck;
12―nAckReverse; 13―Xflag;
14―HostAck; 15―nPeriphRequest;
16―nReverseRequest; 17―IEEE1284Active;
18~25—Each signal ground.

The ECP mode is divided into the following 8 operating stages.

The Design of Interface Communication System Based on SX52BD Single-chip Microcomputer

① Mode negotiation stage. The host puts the ECP capability request value on the data bus, and then sets IEEE 1284 Active to high and HostAck to low. The peripheral should set PeriphClk to low, nPeriphRequest to high, Xflag to high, and nAckReverse to high. The host sets HostClk to low, and then sets HostClk and HostAck to high, indicating that a peripheral compatible with ECP mode has been confirmed. Then, externally set nAckReverse to low, PeriphAck to low, Xflag to high, and PeriphClk to high. The interface enters the setup phase.

② ECP setting stage. The host sets HostAck to low, and externally sets nAckReverse to high to respond to the host. The interface enters the forward idle phase and can start to transmit data.

③Forward idle phase. Externally set PeriphAck to low, the host can start to transmit data when detecting this signal.

④ ECP forward transmission stage. The host puts the data on the data bus and sets HostClk to low. Externally set PeriphAck to high and answer. The host sets HostClk to high, and the peripheral receives data and sets PeriphAck to low to complete the transmission.

This kind of handshake is called interlocked handshake. Interlocking handshake means that each control signal transition is answered by the other party of the interface. In this way, the peripheral can control the transmission time to meet the needs of its operation.

⑤ ECP forward to reverse conversion stage. In the positive idle phase, the host sets the 8-bit data bus to a high impedance state and sets HostAck to low. To wait for the minimum setup time, set nReverseRequest to low. Externally set nAckReverse to low response and enter the reactive idle phase.

The Design of Interface Communication System Based on SX52BD Single-chip Microcomputer

2 Introduction to SX52BD MCU

SX52BD’s on-chip program memory capacity is 4096 bytes, and the data memory capacity is 262×8 bits. SX52BD has 5 8-bit I/O ports A, B, C, D, E, 2 16-bit timers with 8-bit prescaler, 1 universal 8-bit timer with prescaler, and 1 analog comparison Detector, a brownout detector and watchdog timer, an internal RC oscillator. Ports A, B, and C are two-way I/O ports; port B can be used as input for configuration, comparator, and timer 1; port C can be used as input for timer 2; ports D and E are only used for input.

SX52BD has 3 different addressing modes: indirect addressing, direct addressing, and semi-direct addressing. The choice of register addressing mode depends on the value of the 5-bit “fr” in the instruction.

*Indirect mode: fr=00h
*Direct mode: (fr bit 4=0) fr=01h~0Fh
*Semi-direct mode: (fr bit 4=1) fr=10h~1Fh

Since the SX52BD runs at a speed of up to 50MHz, the timing generated by the command operation can fully meet the timing requirements of the ECP protocol, and its I/O port drive capability meets the requirements of the PC. Therefore, there is no need to use any additional hardware circuits to generate timing. This is the concept of virtual peripherals.

3 The realization of ECP communication between SX52BD and PC

Due to the use of virtual peripherals, the hardware circuit structure is extremely simple: just connect the 25 bidirectional I/O ports of the SX52BD single-chip microcomputer to the PC.

The realization of ECP communication is completed by software. After the host has set up the BIOS, it can directly generate the timing required by the hardware through the operation register. The register definition is shown in Table 1.

Table 1 Register definition (base address 0x378)
The Design of Interface Communication System Based on SX52BD Single-chip Microcomputer

The bit definition of the status register dsr is shown in Figure 1, and the bit definition of the control register dcr is shown in Figure 2. The use of ECP to FIFO and DMA is defined in the extended control register ecr, and it is operated only when the speed is high.

The simple ECP protocol is listed below. Figure 3 is the program flow chart on the SX52BD side, and Figure 4 is the program flow chart on the PC side.

Concluding remarks

Generally speaking, because the ECP protocol has perfect functions and simple implementation, it is not very strict on time requirements, and has high application value in many occasions where transmission rate requirements are not particularly high. In addition, the virtual peripherals of the SX series microcontrollers have a wide range of applications.

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