Semiconductor transistor scaling remains unresolved

Philip Wong, a professor of electrical engineering at Stanford University, has written a paper ON advances in silicon scaling with colleagues from the MIT, TSMC, and UC Berkeley institutes. The paper points out that technicians should not only focus on the scaling area of ​​the Transistor pitch, but on the effective density of each successive node.

Translated from – newelectronics

Is Moore’s Law no longer working? It really depends on which aspect.

Philip Wong, a professor of electrical engineering at Stanford University, has written a paper on advances in silicon scaling with colleagues from the MIT, TSMC, and UC Berkeley institutes. The paper points out that technicians should not only focus on the scaling area of ​​the Transistor pitch, but on the effective density of each successive node.

Semiconductor transistor scaling remains unresolved

Looking at other factors, chip manufacturing is going back to basics. In a presentation at the 1975 International Electron Devices Conference (IEDM), Intel executive Gordon Moore decided to regularly double device density over a two-year period. Until then, the industry has been growing at an even faster rate, doubling every year. By 1975, Moore had seen the rate of progress slow.

Moore argues that 2D geometric scaling is just one part of achieving double the functionality at the same cost. He thinks that’s a sizable part, but certainly not all. Significant increases in chip size and improvements in circuit design will meet the remaining requirements, he predicts. At the time, however, fabs were just beginning to take advantage of the scaling factor noted by IBM researcher Robert Dennard: Smaller, more compact transistors could lead to not only cost improvements, but also energy improvements.

The shift to CMOS in the 1980s accelerated this process until the mid-2000s when the industry exhausted most of the benefits of Dennard’s scale. After that, simple 2D scaling will become increasingly cumbersome.

This is most evident in the scaling trend of SRAM in recent years, which has historically been a good guide for density improvements. While it logically kept pace at 28nm, it then started to lag as it struggled to make incremental improvements with different metal pitches and Transistor sizes.

circuit evolution

EDA tool vendor Synopsys will do a demo at IEDM. It will show how the contribution to scaling has changed over the past few years.

What Moore calls “circuit cleverness” has made a comeback, albeit in a different form than originally proposed. This time, its name is Design-Technology Co-Optimization (DTCO). Process engineers can make better trade-offs by having designers advise on the most reasonable process changes to the circuit layout. This is evident in the scaling changes in SRAM, where there is a clear jump in density due to changes in wafer layout.

Wong and the Synopsys team believe that DTCO is a key factor in achieving the 1nm node in the next 10 years. But pure dimensional scaling hasn’t completely disappeared. While there’s not much room for 2D scaling, there’s a lot of potential for 3D scaling, not necessarily stacking chips like a memory standard like HBM. You can subtly think of it as 3D.

One way to take advantage of vertical dimensions is to turn the transistors sideways. This will continue the development of field effect transistors, from a purely planar device, through the vertical contact of the FinFET with the top gate. By wrapping the gate on three sides of the transistor, the fin provides greater electrostatic control of the transistor channel. But beyond 5 nanometers, a full-surround gate structure (Gate-All-Around FET) is required. In fact, a nanosheet through the gate can meet this requirement. Even better, although this adds complexity and cost to the process, you can get more drive current by stacking nanosheets, just like FinFETs typically use two or more fins. Stacking may consume less area than multifin structures.

For FinFET, it should be a more advanced transistor. With each new generation, chipmakers are able to shrink transistor sizes by a factor of 0.7, achieving 15% performance improvement, 50% area gain, 40% power reduction and 35% cost reduction at the device level. A few years ago, the industry transitioned from “old-fashioned” planar mosfets to FinFET transistor architectures in order to maintain this scaling path. In a FinFET, the channel between the source and drain is in the shape of a fin. The gate surrounds this 3D channel and is controlled from 3 sides of the channel. This multi-gate structure eliminates short-channel effects that degrade transistor performance when gate lengths are shortened. Excellent short-channel control is critical because it lays the groundwork for device scaling—allowing for shorter channel lengths and lower operating voltages.

In 2012, the first commercial 22nm FinFETs came out. Since then, FinFET architectures have been improved to increase performance and reduce area. For example, the 3D nature of FinFETs allows for increased fin height, resulting in higher device drive currents in the same package area. Today, the industry is ramping up the production of 10nm/7nm chips that “include” FinFETs. At the cell level at the most advanced nodes, standard cells have a track height of 6T (which is a measure of cell area), and the number of fins per device is as low as 2.

Semiconductor transistor scaling remains unresolved

Vertically stacked nanosheets: an evolutionary step

But FinFETs are expected to fail as they scale below 5nm. FinFET structures in turn do not provide sufficient electrostatic control when reducing gate length. In addition, the evolution to lower track height standard cells requires a transition to single-fin devices, which cannot provide sufficient drive current even if the fin height is further increased.

However, as technology nodes change, the semiconductor industry is in no rush to move to other transistor architectures. Some companies even decided to stay on certain nodes longer. But there are still some applications – such as machine learning, big data analytics and data center servers – that require the latest “universal” CMOS solutions. With this common CMOS solution, the same transistor structure in the same technology node can be used to perform all functions on the chip.

Here, vertically stacked nanosheet transistors can come to the rescue. They can be considered as a natural evolution of FinFET devices. Imagine putting a FinFET on its side and then dividing it into individual horizontal slices that make up the channel. Now, a gate completely surrounds the channel. Compared to multi-gate FinFETs, this gate-all-in-one feature of nanosheet provides better channel control capability. At the same time, a more optimal distribution of channel cross-sections in the 3D volume optimizes the effective drive per unit area.

A barrier to nanosheet scaling is the need to separate between the n- and p-channel devices of a CMOS pair. But Imec came up with a forksheet last year. This consists of a common pillar with n- and p-doped flakes stacked on top of each other. At the same time, you have a complete CMOS inverter built into a single transistor structure, saving about 30% of the area.

Harvesting energy from logic cells takes up valuable area. Imec’s proposal at the 2018 Very Large Scale Integration (VLSI) Symposium was to bury the power rails in the silicon surface. The next step is CFET (nanosheet field effect transistor): nFET and pFET share a gate electrode as a signal input, a drain as a signal output, and the source electrodes are grounded and powered respectively. The device size can be flexibly adjusted to meet different chip performance requirements.

At the upcoming IEDM, Intel engineers will describe their views on nanosheet-based CFET-type structures. The combined transistor uses epitaxy to build a vertically stacked source-drain structure with threshold voltages individually tuned for the two transistors. While the gates in this work are relatively long at around 30nm, the Intel team hopes to achieve significant wafer size reduction through self-aligned stacking.

According to Synopsys’ calculations, the CFET does a lot of work on the SRAM, although it requires some DTCO. One downside of CFETs is that stacking introduces another form of variability, but again, design tweaks will help address this. For example, the most compact structures do not rely entirely on full-surround gate transistors. Instead, it incorporates a dummy p-channel transistor with a three-sided gate for good enough write behavior.

main problem

Even with increased transistor density, a major problem in chip design is parasitic resistance and capacitance in metal interconnects. This could force future production processes away from copper as the main feedstock and towards more exotic metals such as ruthenium.

Intel proposes an alternative based on design, that while it may seem desirable to cut resistors and Capacitors together, not all circuit paths will benefit in the same way.

A single path can benefit from individually tuned resistors and capacitors. That’s what guided Intel’s findings on what’s called an interleaved interconnect.

Semiconductor transistor scaling remains unresolved

Instead of making every parallel line the same, this staggered approach alternates tall and short lines, with the short lines on higher stacks of insulator material. This reduces the net effective capacitance between the lines. In reality, the high line would be more disturbed, and similar effects would be spaced farther apart.

These DTCO-inspired designs are more complex and will drive up wafer costs: an average of 13 percent per node, Synopsys said. But the effective density is still feasible at the 1-nanometer node, and it is still possible to reduce the cost per transistor by 32% per node.

This isn’t yesterday’s Moore’s Law, but the trend should continue for about a decade. How many companies can have such a large business volume to justify it remains another question.

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