[Introduction]Electronic equipment is increasingly connected to the grid, which increases the probability of distortion of the grid and makes the distribution network prone to problems. To alleviate these problems, power supply designs require advanced power factor correction (PFC) circuits to meet stringent power factor (PF) standards.
The most commonly used topology for power factor correction is boost PFC, but the advent of wide bandgap (WBG) semiconductors such as GaN and SiC has driven the realization of bridgeless topologies such as totem-pole PFC, while advanced The totem-pole controller further simplifies the control of complex designs such as interleaved totem-pole PFCs. This article compares the use of three topologies in different applications, including interleaved boost PFC, bridgeless totem-pole PFC, and interleaved totem-pole PFC.
Interleaved Boost PFC
Interleaved boost PFC is the most common power factor correction topology. This topology includes a boost converter (see Figure 1) in addition to using a rectifier diode bridge to convert the AC voltage to a DC Voltage. The boost converter boosts the voltage to a higher value, which reduces the output voltage ripple while shaping the current into a sine wave.
Figure 1: Interleaved boost PFC schematic
Power factor correction can be achieved with only one boost converter, but designers often use two or more converters in parallel that are phase-shifted with respect to each other. This interleaved connection improves efficiency while reducing input current ripple.
Bridgeless Totem Pole PFC
The application of new semiconductor materials, especially silicon carbide (SiC), to power switches can enable designs that were previously infeasible due to the thermal and electrical properties of silicon. One of them is the bridgeless totem-pole topology, which integrates rectification and boost stages and provides two switching branches operating at different frequencies (see Figure 2).
Figure 2: Schematic of a bridgeless totem-pole PFC
The first branch, called the slow branch (SD1 and SD2), commutates at the grid frequency (eg between 50Hz and 60Hz). It uses traditional silicon switches, which are mainly responsible for rectifying the input voltage. The second branch, called the fast branch (Q1 and Q2), mainly shapes the current while boosting the voltage, and this branch needs to switch at an extremely high frequency (~100kHz). High-power switching with higher frequencies imposes greater thermal and electrical stress ON the switches, and converters need to utilize wide-bandgap Semiconductor devices such as SiC and GaN mosfets to operate safely and efficiently.
This topology typically improves performance compared to an interleaved boost converter. But additional active switches complicate the control circuit, a problem that can often be mitigated with an integrated totem-pole controller.
Staggered Totem Pole PFC
To increase the efficiency of a bridgeless totem-pole PFC, additional high-frequency branches can be added to create a staggered totem-pole PFC. This extra branch reduces the converter’s output voltage ripple and distributes the converter’s power requirements equally across all branches, minimizing layout size and overall cost.
Figure 3: Interleaved bridgeless totem-pole PFC schematic
Comparative Experimental Design of PFC Topologies
Operating parameters
To compare topologies in different cases, we developed a series of simulation models for the two power levels. The same system specifications were also used to make the results comparable (see Table 1).
Table 1: System Specifications
parameter comparison
The key parameters defined for topology comparison are described below.
Input Current Ripple (ΔIIN): ΔIIN represents the amount of change in the input current, obtained by measuring the difference between the maximum and minimum values of the input current during a single switching cycle. ΔIIN is calculated using equation (1):
Current Total Harmonic Distortion (THDI): THDI is obtained by measuring the harmonic distortion present in the input current without a filter. THDI can be estimated using Equation (2):
Inductive Energy Index (IEI) and Capacitive Energy Index (CEI): These indices provide information on the converter’s inductance and capacitance requirements per unit of power (see Equations 3 and 4), which are closely related to the final size and cost of the component. IEI can be calculated using formula (3):
CEI can be estimated using equation (4):
Total Switching Power Index (TSP): TSP compares the voltage and current stress per power cell (similar to silicon equivalent area) of a converter semiconductor device. TSP is closely related to the final cost of the silicon device in the converter. TSP can be calculated using Equation (5):
Efficiency (ƞ): Efficiency (ƞ): Efficiency is used to compare the energy lost in power factor correction circuits. Efficiency can be derived by calculating the ratio between the input power consumed by the circuit and the power available at the output (see Equation 5). It specifies the topology with the least power consumption. Efficiency can be estimated using Equation (6):
Comparison Results of Totem Pole PFC and Interleaved Boost PFC
The first test simulates all three topologies for a 300W application, a power level typically used for computer power supplies. The second test simulated the topology at a 3kW application, a high power level typically used in applications such as electric vehicle charging.
Common characteristics of each topology can be derived from topology comparison. However, the performance of these designs is highly dependent on the selected device and its operating parameters. Therefore, designers must think carefully, choose a design rationally, and carefully optimize it for the application. To illustrate this, we analyze the power loss considering only device losses, similar devices can be used for all topologies.
Power Advantages of Totem Pole PFC
The first key finding of the topology comparison is that the totem-pole PFC does not contain a rectifier bridge, thus reducing the number of switching devices. The diode bridge in the boost converter is always on, so conduction losses are the key factor affecting the efficiency of this topology. At low power, the current in the converter is relatively small, so most of the power dissipation occurs during switching operations. This is why boost and totem-pole PFC topologies have similar efficiencies in 300W applications (see Figure 4). The losses in conventional and interleaved totem-pole designs are not much different, and for simplicity we compare the efficiency between an interleaved boost converter and a totem-pole converter.
Figure 4: Power Loss in a 300W Design
When operating at 3kW, the current in the circuit increases significantly, and there is a significant conduction loss in the boost topology due to the high equivalent resistance in the rectifier diodes. Therefore, in high-power applications, totem-pole PFCs are much more efficient (see Figure 5).
Figure 5: Power Loss in a 3kW Design
Efficiency improvements for interleaved boost and totem-pole PFC topologies
Another key point in the comparison of boost and totem-pole PFC topologies is the comparison of operating modes. Totem-pole topologies typically operate in continuous conduction mode (CCM), while interleaved boost topologies operate in critical conduction mode (CrCM). CCM operation can significantly reduce Inductor current ripple and THDI, while CrCM results in a lower inductive energy index (IEI) due to the smaller required inductance (see Figure 6).
Figure 6: Input Current Simulation Results
However, the increased THDI means that the boost PFC requires a larger input filter to meet power quality requirements, which diminishes the benefits of eliminating the need for an Inductor, such as cost and size reductions. Furthermore, the switching current in CrCM is much larger than that in CCM, which increases the voltage and current stress on the switching element (see Figure 7).
Figure 7: Simulation results of the current flowing through the Inductor
Paralleling multiple converters can distribute the current stress across multiple phases, improving performance. By itself, the efficiency and performance of a single non-interleaved boost converter cannot be compared to a totem-pole PFC. But by interleaving multiple boost converters, performance can be significantly improved. Therefore, the interleaved boost topology is a valid choice for mid-range power applications, such as the 300W example mentioned above (see Figure 8).
However, at high power, the efficiency of the interleaved boost converter is difficult to match with the totem-pole topology. Also, for 3kW or higher power applications, even totem pole converters can benefit from interleaved connections. The interleaved connection divides the current between the two branches, thereby halving the inductance of each branch, which relaxes the power switching requirements while also reducing input current ripple.
Figure 8: Inductor current in an interleaved boost PFC
Table 2 summarizes the different parameters of the three PFC topologies.
Table 2: PFC topology comparison simulation results
in conclusion
This article illustrates the key characteristics of interleaved boost, totem pole, and interleaved totem pole PFC topologies through simulation and comparison of key parameters to help designers choose the best topology for their application.
The simplicity of the boost PFC topology makes it the preferred solution for most designers. However, boost PFCs are less efficient in high-power applications, so in this case a totem-pole PFC topology may be preferable despite the added complexity. Furthermore, the introduction of an integrated totem-pole controller such as the MPF32010 can greatly simplify the implementation of totem-pole PFC converters.