“mosfet selection for DC/DC switching controllers is a complex process. Just considering the voltage and current rating of the MOSFET is not enough to select the right MOSFET. To maintain a MOSFET within specification, a balance must be struck between low gate charge and low ON-resistance. In a multi-load power system, the situation becomes more complicated.
MOSFET selection for DC/DC switching controllers is a complex process. Just considering the Voltage and current rating of the MOSFET is not enough to select the right MOSFET. To maintain a MOSFET within specification, a balance must be struck between low gate charge and low on-resistance. In a multi-load power system, the situation becomes more complicated.
Figure 1 – Schematic of a Buck Synchronous Switching Regulator
DC/DC switching power supplies are widely used in many modern Electronic systems due to their high efficiency. For example, a step-down synchronous switching Regulator with both a high-side FET and a low-side FET is shown in Figure 1. The two FETs switch according to the duty cycle set by the controller to achieve the desired output voltage. The duty cycle equation for a buck regulator is as follows:
1) Duty cycle (high side FET, top tube) = Vout/(Vin*efficiency)
2) Duty cycle (low side FET, down side) = 1 C DC (high side FET)
The FET may be integrated into the same chip as the controller, enabling one of the simplest solutions. However, in order to provide high current capability and/or achieve higher efficiency, the FET needs to always be an external component of the controller. This allows for maximum heat dissipation because it physically isolates the FETs from the controller and provides the most flexibility in FET selection. The downside is that the FET selection process is more complicated because there are many factors to consider.
A common question is “Why not have this 10A FET also be used in my 10A design?” The answer is that this 10A current rating is not suitable for all designs.
Factors to consider when choosing a FET include voltage rating, ambient temperature, switching frequency, controller drive capability, and thermal component area. The key point is that if the power dissipation is too high and the heat dissipation is not enough, the FET can overheat and catch fire. We can estimate the junction temperature of a FET using the package/thermal components ThetaJA or thermistor, FET power dissipation, and ambient temperature as follows:
3) Tj = ThetaJA * FET power dissipation (PdissFET) + ambient temperature (Tambient)
It requires calculating the power dissipation of the FET. This power dissipation can be divided into two major components: AC and DC losses. These losses can be calculated by the following equations:
4) AC loss: AC power consumption (PswAC) = ? * Vds * Ids * (trise + tfall)/Tsw
where Vds is the input voltage of the high-side FET, Ids is the load current, trise and tfall are the rise and fall times of the FET, and Tsw is the switching time of the controller (1/switching frequency).
5) DC Loss: PswDC = RdsOn * Iout * Iout * Duty Cycle
Among them, RdsOn is the on-resistance of the FET, and Iout is the load current of the buck topology.
Other causes of losses include output parasitic capacitance, gate losses, and body diode losses due to conduction during the dead time of the low-side FET, but in this article we will focus on AC and DC losses.
When the switch voltage and current are both non-zero, AC switching losses occur during the transition between the switch on and off. The highlighted part in Figure 2 shows this situation. According to Equation 4), one way to reduce this loss is to shorten the rise and fall times of the switch. This can be achieved by choosing a lower gate charge FET. Another factor is the switching frequency. The higher the switching frequency, the greater the percentage of switching time spent in the rise and fall transition region shown in Figure 3. Therefore, higher frequencies mean greater AC switching losses. So, another way to reduce AC losses is to reduce the switching frequency, but this requires a larger and often more expensive Inductor to keep the peak switch current within specification.
Figure 2 – AC Loss Diagram
Figure 3 – Effect of Switching Frequency on AC Losses
The DC loss occurs when the switch is in the on state, due to the on-resistance of the FET. This is a very simple I2R loss formation mechanism, as shown in Figure 4. However, the on-resistance varies with the FET junction temperature, which complicates the situation. Therefore, when using equations 3), 4), and 5) to accurately calculate the on-resistance, an iterative method must be used, taking into account the temperature rise of the FET. One of the easiest ways to reduce DC losses is to choose a low on-resistance FET. In addition, the magnitude of the DC losses is proportional to the percent on-time of the FET, which is the high-side FET controller duty cycle plus 1 minus the low-side FET duty cycle, as previously described. From Figure 5, we can know that longer on-time means greater DC switching losses, therefore, DC losses can be reduced by reducing the on-time/FET duty cycle. For example, if an intermediate DC rail is used, and the input voltage can be modified, the designer might be able to modify the duty cycle.
Figure 4 – DC Loss Diagram
Figure 5 – Effect of Duty Cycle on DC Losses
Although choosing a FET with low gate charge and low on-resistance is an easy solution, there are some tradeoffs and tradeoffs between these two parameters. Low gate charge generally means smaller gate area/fewer transistors in parallel, and thus high on-resistance. On the other hand, using larger/more parallel transistors generally results in lower on-resistance and thus more gate charge. This means that FET selection must balance these two conflicting specifications. In addition, the cost factor must also be considered.
Low duty cycle designs imply high input voltage, and for these designs, the high-side FET is off most of the time, resulting in low DC losses. However, high FET voltages result in high AC losses, so FETs with low gate charge can be selected, even with high on-resistance. The low-side FET is on most of the time, but has minimal AC losses. This is because the voltage of the low-side FET during on/off is very low due to the FET body diode. Therefore, a low on-resistance FET needs to be chosen, and the gate charge can be high. Figure 7 shows the above situation.
Figure 12 – Power system showing input, mid-rail, point-of-load (POL) supply, and load. The different options for the mid-rail voltage are 28V (using input power directly), 12V and 5V. This results in a different duty cycle of the POL regulator.
Figure 13. Power supply design graph showing the effect of mid-rail voltage on power system efficiency, size, and cost.