Microchip unveils 1.6T Secure Ethernet PHY

As 112G PAM4 connectivity expands beyond cloud data center and telecom switches and routers to enterprise Ethernet switching platforms, Microchip Technology Inc. has launched its META-DX2 Ethernet PHY (physical layer) portfolio to meet this growing demand. The company has claimed the new META-DX2+ PHYs as the industry’s first solution to integrate 1.6T (terabits per second) of line-rate end-to-end encryption and port aggregation for enterprise Ethernet switches, security appliances, cloud interconnect routers, and optical transport systems.

Microchip unveils 1.6T Secure Ethernet PHY

(Source: Microchip Technology)

The four new META-DX2+ PHYs support Ethernet data rates from 1G to 800G and include advanced features including encryption, port aggregation, 112G PAM4 SerDes, and Class C/D precision timing. The portfolio also includes footprint-compatible retimers. Together, these devices enable the addition of MACsec and IPsec encryption based ON a common board design and software development kit, said Microchip.

The META-DX2+’s configurable 1.6T datapath architecture is said to outperform the closest competitors by 2× in total gearbox capacity and hitless 2:1 protection switch mux modes enabled by the unique ShiftIO capability. It also features XpandIO port aggregation capabilities, which optimize router/switch port utilization when supporting low-rate traffic, said Microchip. The devices support IEEE 1588 Class C/D Precision Time Protocol (PTP) for accurate nanosecond timestamping required for 5G and enterprise business critical services.

Key META-DX2+ capabilities cited include:

  • Dual 800 GbE, quad 400 GbE, and 16x 100/50/25/10/1 GbE MAC/PHY
  • Integrated 1.6T MACsec/IPsec engines that offload encryption from packet processors so systems can more easily scale up to higher bandwidths with end-to-end security
  • Greater than 20% board savings compared to competing solutions that require two devices to deliver the same 1.6T gearbox and hitless 2:1 mux modes
  • XpandIO enables port aggregation of low-rate Ethernet clients over higher speed Ethernet interfaces, optimized for enterprise platforms
  • ShiftIO feature combined with a highly configurable integrated crosspoint enables flexible connectivity between external switches, processors, and optics
  • Device variants with 48 or 32 Long Reach (LR) capable 112G PAM4 SerDes including programmability to optimize power vs. performance
  • Support for Ethernet, OTN, Fibre Channel and proprietary data rates for AI/ML applications

Like the META-DX2L retimer, the META-DX2+ PHYs can be used with Microchip’s PolarFire FPGAs, the ZL30632 high-performance PLL, oscillators, Voltage regulators, and other components that have been pre-validated as a system.

Microchip’s second-generation Ethernet PHY SDK supports all META-DX2L and META-DX2+ PHY devices. The Open Compute Project (OCP) Switch Abstraction Interface (SAI) PHY extensions are included to enable agnostic support of the META-DX2 PHYs in a range of network operating systems (NOS) that support SAI, said the company.

Sampling of the META-DX2+ family is expected to start in the fourth quarter of 2022. Microchip will be exhibiting the META-DX2L PHY device, which started sampling in the fourth quarter of 2021, in the Optical Internetworking Forum (OIF) booth at the European Conference on Optical Communication (ECOC), September 18-22, 2022, in Basel Switzerland.

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