# How to design a high-precision analog-to-digital conversion ADC?

Essentially, the main difference between analog chips and digital chips is the difference in signal processing. As the name suggests, analog chips process analog signals, while digital chips process digital signals. The analog signal changes continuously over time, such as temperature, humidity, sound, speed, and so ON. Their biggest feature is that there are countless different values ​​within a certain time range.

Author: Lao Shi

I haven’t talked about analog chips for a while, and today we will talk about analog chips, especially the analog-to-digital conversion chip ADC.

1. What is ADC

Essentially, the main difference between analog chips and digital chips is the difference in signal processing. As the name suggests, analog chips process analog signals, while digital chips process digital signals. The analog signal changes continuously over time, such as temperature, humidity, sound, speed, and so on. Their biggest feature is that there are countless different values ​​within a certain time range.

In contrast, a digital signal is a bunch of discrete values, such as the binary 0101 used in computers. Since the Transistor has two states of on and off, it can naturally represent the values ​​of 0 and 1. There is no way for a Transistor to achieve a state like 10% on or 31.5% off, so it is a digital signal.

In order to connect the two independent fields of analog and digital, it is necessary to use two kinds of chips as a bridge, one is the analog-to-digital conversion chip ADC, and the other is the digital-to-analog conversion chip DAC.

As the name implies, the analog-to-digital conversion chip ADC is used to convert analog signals into digital signals, and the analog-to-digital conversion DAC is just the other way round, converting digital signals into analog signals. However, in practical applications, ADC accounts for a higher proportion. Data shows that 80% of the applications where analog-to-digital conversion is applied are ADCs. Especially in the digital society, almost everything has been digitized, which is convenient for subsequent processing, transmission and storage.

Many friends may think that it’s just that the analog signal is converted into a digital signal, it sounds like it is not difficult. In fact, the ADC chip is the most difficult analog chip, and it may not even be one of them. At the top conference ISSCC in the field of semiconductors and integrated circuits, that is, the International Solid-State Circuits Conference, there are quite a few articles on ADC design.

2. How to design and optimize ADC

So, how exactly is the analog-to-digital conversion ADC implemented? Simply put, several processes such as sampling (Sampling), quantization (Quantization), and encoding (Encoding) are required. In other words, we first need to sample this signal and record the voltage value of the signal at regular intervals. The collected value will be quantized, converted into the corresponding digital signal value, and finally expressed by some kind of code, such as complement code, gray code, and so on.

ADC has many parameter indicators, of which there are two common parameters, one is ADC sampling rate (sampling rate) or data rate (data rate), and the other is resolution (resolution). The sampling rate is well understood, that is, how many samplings can be done per unit time, and the more sampling points, the better the original signal can be restored.

Resolution is defined as the smallest change in the value of the input signal. This smallest change in value will change a code value of the ADC digital output value. In the case that the ADC has the same input range, the higher the resolution, the smaller the minimum change represented by a code value. If our ADC has 3 bits, then the entire Voltage range can be divided into 2^3=8 parts. If the voltage range is 0-10V, then each part represents 1.25V. In other words, if the voltage change is less than this value, then the ADC cannot capture this small change. The important thing to note is that ADC resolution and ADC accuracy are two completely different concepts. There are many specific implementation forms of ADC, the common ones include successive approximation ADC (SAR), and there is also a Delta-Sigma ADC. For example, a common successive approximation ADC mainly integrates a voltage comparator, a register, a DAC, and some control circuits in the circuit. Its essence is to use binary search to determine the digital signal corresponding to the analog voltage. That is, at the beginning, the input voltage is compared with half of the reference voltage. If the input voltage is larger, then compare with three-quarters of the reference voltage. On the contrary, if the input voltage is smaller, it is compared with a quarter of the reference voltage. And so on, until the comparison is complete.

3. ADC drive design

However, even the most basic ADC is not simple in actual engineering applications, so supporting resource support is particularly important. For example, ADCs often cannot work independently. They need to cooperate with other external circuits to function. One of the most important external circuits is the drive circuit.

As mentioned earlier, the ADC needs to sample, quantize and encode the input signal, and output an N-bit digital signal. These operations are usually completed in one cycle of the digital clock. This means that during the sampling process, the input signal should remain unchanged. This is a bit similar to the hold time of a clock in a digital signal.

Inside the ADC, its input actually contains a switch and a Capacitor array, which is usually equivalent to a switch and a sampling capacitor. When the switch is closed, the capacitor is charged; after it is charged, the switch is opened, and the comparator and the DAC cooperate with each other to complete the sampling and quantization operation of the ADC at this time.

This is the problem. First of all, if the performance requirements of the ADC are relatively high, for example, if its sampling frequency is required to be high, then the time to charge the capacitor inside the ADC will be very short. For example, if the sampling frequency is 1 million samples per second, then the charging time, that is, the capture time (TACQ) may only be 300 nanoseconds. If no circuit is added to the input as a driver, it will basically not be able to meet the demand for such a high sampling frequency. So in response to this problem, we usually add an operational Amplifier to the ADC front end as a driver, so that sufficient charge can be provided to the sampling capacitor within a short sampling time. This is not over yet. Although we can directly connect the op amp and ADC directly, we rarely design this way in practical applications. Because when the sampling frequency is very high, a very high bandwidth op amp is required if it is directly connected to the op amp. In addition, it can be seen from the simulation that when the switch is switched, the initial conversion may generate a large instantaneous current, and the drive circuit needs to be able to sample the ADC internals within a short ADC capture time (TACQ) The capacitor is fully charged.

In order to meet these conditions and avoid large instantaneous currents, we can add an RC circuit before the ADC. We have learned in the university circuit that the RC circuit is used for filtering, but its main function here is to use this extra capacitor to achieve faster charging. The op amp can fill this capacitor, and then when the ADC internal switch is closed, charge the ADC internal capacitor through this capacitor. Of course, in addition to this capacitor, part of the charge also comes from the front-end op amp. This RC circuit is also called a charge bucket filter circuit, which can effectively reduce the bandwidth requirements of the front-end op amp, so we can choose a lower bandwidth and lower cost ordinary op amp to meet the design needs. At the same time, it also eliminates the initial instantaneous current and greatly improves the stability of the circuit.

The question is again, how to determine the specific size and indicators of these amplifiers and RC circuits? There are two methods here. One is to derive through theoretical formulas. There is a very detailed derivation process on the Internet. According to ADC indicators, such as resolution, sampling rate, reference voltage, etc., you can derive the required RC step by step. Parameter data of the circuit and op amp. After seeing these things, I really couldn’t help but think of the fear of being dominated by it when I was learning analog electronics…

Of course, there is another method, which is to perform simulation calculations through ready-made design tools and simulation tools. For example, Texas Instruments TI provides a series of related tools to simplify all the above calculation processes. At the beginning, you can select the corresponding device according to the performance indicators of the ADC, and then use the ADC SAR Drive tool to directly calculate the value of the resistance and capacitance, and get the corresponding performance indicators.

In order to further simplify the design process, TI not only provides design tools, but also a complete ecosystem to integrate these tools. Taking SAR drive design as an example, TI provides many classic ADC circuit design solutions. For example, this “high-voltage battery monitor circuit” teaches us step by step from design description goals, to how to choose suitable devices, and how to model and simulate. , And get the ideal performance index. And in the design process, you can review the “TI High Precision Laboratory” video series as a reference at any time. Specific to this circuit, we can always check the method of selecting the charge bucket filter introduced in the “High Precision Laboratory”, and provide good stability and stability for the amplifier, gain setting and data converter in this example. Communication performance. We can also directly download the design file of this circuit, and modify the design according to the requirements. 4. Noise in PADC design

As mentioned in the previous article, one of the biggest problems with analog chips is that they are susceptible to interference. In fact, there are too many places where analog signals can be interfered. From the electromagnetic radiation EMI mentioned before, to the design defects of the circuit board, the change of the power supply voltage, and the various changes in the surrounding environment, they may actually be affected. The analog chip and the analog circuit cause interference and cause errors.

For the ADC, in addition to these external factors and interference, it itself will also introduce errors, which is usually called quantization error. That is to say, when we quantify a continuously changing analog quantity into a discretely changing digital quantity, this kind of error will inevitably be introduced. No matter how fine the granularity of our division, how small the division, this quantification error will exist.

Let me talk about theory first, for an N-bit ADC, the voltage range represented by each bit can be obtained by this formula Among them, FSR is the voltage range supported by ADC. Then the smallest voltage change that can be distinguished in this ADC is half of the LSB. For example, a 3-bit ADC, the input voltage varies from 0 to 8V. Then its LSB is 8/2^3 = 1V, and the minimum voltage change that can be distinguished is 1/2V. That is to say, when the input voltage is between 0-0. 5V, the output is actually 0, when from 0.5-1.5, the output is always 1, and so on. So the output is actually a step curve.

Combined with the aforementioned environmental noise, also known as thermal noise (thermal), then the total noise of an ADC is the square sum of thermal noise and quantization noise. Is it a bit of an upside to see here, this is actually just the beginning. For a given ADC, we have to quantify and measure its two noises, so that we can better and target the design of the entire system including the ADC.

Take the Delta-Sigma ADC as an example. These two types of noise depend on the resolution, reference voltage, and output rate of the ADC. For a system that includes an ADC, this noise analysis is more complicated. In a typical analog-to-digital conversion system, it usually contains various analog noise filters, operational amplifiers, ADCs, and digital filters, FPGAs, MCUs and other analog digital chips that process digital signals, which also constitute a signal chain. . To analyze the noise of this signal chain, we must not only do noise analysis on the ADC itself, but also examine the noise of each component in the entire signal chain and the mutual influence between all these components. This thing sounds complicated, but we can use the effective noise bandwidth of the signal chain (Effective Noise Bandwidth) to quantify this analysis process. Of course, we also need a series of tools, software and reference materials to help us do quantitative analysis.

In fact, much of the previous content comes from TI’s e-book “Basics of High-Accuracy ADC Noise Analysis.” This book combines the design and practical experience of a large number of TI engineers, and introduces in detail the noise sources of ADCs, how to quantify and analyze them, and how to effectively design circuits to optimize the noise performance of ADCs. This book is very easy to understand, and it also takes into account the depth of technology. It is highly recommended to everyone.

In the aforementioned TI “High Precision Laboratory” tutorial, in addition to the drive circuit design and noise analysis introduced here, there are also the most basic ADC foundation, the principle and comparison of SAR and Delta-sigma ADC, error analysis, Low-power design, high-speed design, etc., are very comprehensive. There are supporting exercises after each video to facilitate us to consolidate the learning results. I think whether you are a novice or a veteran of analog electronics, you can find content that suits you.

“High-precision laboratory” and ADC circuit design guide manual are part of TI ADC toolbox. There is also “Analog Engineer Pocket Reference Book”, which can be used to quickly find and calculate various signal chain tuning methods, including Op amp bandwidth, stability, etc. These design resources can be used in conjunction with ADC analog engineer calculator, TI TINA and Pspice for TI to form a one-stop design experience. I put the links to these contents in the reference materials below. Friends who want to learn this knowledge must remember to start here.

Author: Lao Shi

I haven’t talked about analog chips for a while, and today we will talk about analog chips, especially the analog-to-digital conversion chip ADC.

1. What is ADC

Essentially, the main difference between analog chips and digital chips is the difference in signal processing. As the name suggests, analog chips process analog signals, while digital chips process digital signals. The analog signal changes continuously over time, such as temperature, humidity, sound, speed, and so on. Their biggest feature is that there are countless different values ​​within a certain time range.

In contrast, a digital signal is a bunch of discrete values, such as the binary 0101 used in computers. Since the Transistor has two states of on and off, it can naturally represent the values ​​of 0 and 1. There is no way for a transistor to achieve a state like 10% on or 31.5% off, so it is a digital signal.

In order to connect the two independent fields of analog and digital, it is necessary to use two kinds of chips as a bridge, one is the analog-to-digital conversion chip ADC, and the other is the digital-to-analog conversion chip DAC.

As the name implies, the analog-to-digital conversion chip ADC is used to convert analog signals into digital signals, and the analog-to-digital conversion DAC is just the other way round, converting digital signals into analog signals. However, in practical applications, ADC accounts for a higher proportion. Data shows that 80% of the applications where analog-to-digital conversion is applied are ADCs. Especially in the digital society, almost everything has been digitized, which is convenient for subsequent processing, transmission and storage.

Many friends may think that it’s just that the analog signal is converted into a digital signal, it sounds like it is not difficult. In fact, the ADC chip is the most difficult analog chip, and it may not even be one of them. At the top conference ISSCC in the field of semiconductors and integrated circuits, that is, the International Solid-State Circuits Conference, there are quite a few articles on ADC design.

2. How to design and optimize ADC

So, how exactly is the analog-to-digital conversion ADC implemented? Simply put, several processes such as sampling (Sampling), quantization (Quantization), and encoding (Encoding) are required. In other words, we first need to sample this signal and record the voltage value of the signal at regular intervals. The collected value will be quantized, converted into the corresponding digital signal value, and finally expressed by some kind of code, such as complement code, gray code, and so on.

ADC has many parameter indicators, of which there are two common parameters, one is ADC sampling rate (sampling rate) or data rate (data rate), and the other is resolution (resolution). The sampling rate is well understood, that is, how many samplings can be done per unit time, and the more sampling points, the better the original signal can be restored.

Resolution is defined as the smallest change in the value of the input signal. This smallest change in value will change a code value of the ADC digital output value. In the case that the ADC has the same input range, the higher the resolution, the smaller the minimum change represented by a code value. If our ADC has 3 bits, then the entire voltage range can be divided into 2^3=8 parts. If the voltage range is 0-10V, then each part represents 1.25V. In other words, if the voltage change is less than this value, then the ADC cannot capture this small change. The important thing to note is that ADC resolution and ADC accuracy are two completely different concepts. There are many specific implementation forms of ADC, the common ones include successive approximation ADC (SAR), and there is also a Delta-Sigma ADC. For example, a common successive approximation ADC mainly integrates a voltage comparator, a register, a DAC, and some control circuits in the circuit. Its essence is to use binary search to determine the digital signal corresponding to the analog voltage. That is, at the beginning, the input voltage is compared with half of the reference voltage. If the input voltage is larger, then compare with three-quarters of the reference voltage. On the contrary, if the input voltage is smaller, it is compared with a quarter of the reference voltage. And so on, until the comparison is complete.

3. ADC drive design

However, even the most basic ADC is not simple in actual engineering applications, so supporting resource support is particularly important. For example, ADCs often cannot work independently. They need to cooperate with other external circuits to function. One of the most important external circuits is the drive circuit.

As mentioned earlier, the ADC needs to sample, quantize and encode the input signal, and output an N-bit digital signal. These operations are usually completed in one cycle of the digital clock. This means that during the sampling process, the input signal should remain unchanged. This is a bit similar to the hold time of a clock in a digital signal.

Inside the ADC, its input actually contains a switch and a capacitor array, which is usually equivalent to a switch and a sampling capacitor. When the switch is closed, the capacitor is charged; after it is charged, the switch is opened, and the comparator and the DAC cooperate with each other to complete the sampling and quantization operation of the ADC at this time.

This is the problem. First of all, if the performance requirements of the ADC are relatively high, for example, if its sampling frequency is required to be high, then the time to charge the capacitor inside the ADC will be very short. For example, if the sampling frequency is 1 million samples per second, then the charging time, that is, the capture time (TACQ) may only be 300 nanoseconds. If no circuit is added to the input as a driver, it will basically not be able to meet the demand for such a high sampling frequency. So in response to this problem, we usually add an operational amplifier to the ADC front end as a driver, so that sufficient charge can be provided to the sampling capacitor within a short sampling time. This is not over yet. Although we can directly connect the op amp and ADC directly, we rarely design this way in practical applications. Because when the sampling frequency is very high, a very high bandwidth op amp is required if it is directly connected to the op amp. In addition, it can be seen from the simulation that when the switch is switched, the initial conversion may generate a large instantaneous current, and the drive circuit needs to be able to sample the ADC internals within a short ADC capture time (TACQ) The capacitor is fully charged.

In order to meet these conditions and avoid large instantaneous currents, we can add an RC circuit before the ADC. We have learned in the university circuit that the RC circuit is used for filtering, but its main function here is to use this extra capacitor to achieve faster charging. The op amp can fill this capacitor, and then when the ADC internal switch is closed, charge the ADC internal capacitor through this capacitor. Of course, in addition to this capacitor, part of the charge also comes from the front-end op amp. This RC circuit is also called a charge bucket filter circuit, which can effectively reduce the bandwidth requirements of the front-end op amp, so we can choose a lower bandwidth and lower cost ordinary op amp to meet the design needs. At the same time, it also eliminates the initial instantaneous current and greatly improves the stability of the circuit.

The question is again, how to determine the specific size and indicators of these amplifiers and RC circuits? There are two methods here. One is to derive through theoretical formulas. There is a very detailed derivation process on the Internet. According to ADC indicators, such as resolution, sampling rate, reference voltage, etc., you can derive the required RC step by step. Parameter data of the circuit and op amp. After seeing these things, I really couldn’t help but think of the fear of being dominated by it when I was learning analog electronics…

Of course, there is another method, which is to perform simulation calculations through ready-made design tools and simulation tools. For example, Texas Instruments TI provides a series of related tools to simplify all the above calculation processes. At the beginning, you can select the corresponding device according to the performance indicators of the ADC, and then use the ADC SAR Drive tool to directly calculate the value of the resistance and capacitance, and get the corresponding performance indicators.

In order to further simplify the design process, TI not only provides design tools, but also a complete ecosystem to integrate these tools. Taking SAR drive design as an example, TI provides many classic ADC circuit design solutions. For example, this “high-voltage battery monitor circuit” teaches us step by step from design description goals, to how to choose suitable devices, and how to model and simulate. , And get the ideal performance index. And in the design process, you can review the “TI High Precision Laboratory” video series as a reference at any time. Specific to this circuit, we can always check the method of selecting the charge bucket filter introduced in the “High Precision Laboratory”, and provide good stability and stability for the amplifier, gain setting and data converter in this example. Communication performance. We can also directly download the design file of this circuit, and modify the design according to the requirements. 4. Noise in PADC design

As mentioned in the previous article, one of the biggest problems with analog chips is that they are susceptible to interference. In fact, there are too many places where analog signals can be interfered. From the electromagnetic radiation EMI mentioned before, to the design defects of the circuit board, the change of the power supply voltage, and the various changes in the surrounding environment, they may actually be affected. The analog chip and the analog circuit cause interference and cause errors.

For the ADC, in addition to these external factors and interference, it itself will also introduce errors, which is usually called quantization error. That is to say, when we quantify a continuously changing analog quantity into a discretely changing digital quantity, this kind of error will inevitably be introduced. No matter how fine the granularity of our division, how small the division, this quantification error will exist.

Let me talk about theory first, for an N-bit ADC, the voltage range represented by each bit can be obtained by this formula Among them, FSR is the voltage range supported by ADC. Then the smallest voltage change that can be distinguished in this ADC is half of the LSB. For example, a 3-bit ADC, the input voltage varies from 0 to 8V. Then its LSB is 8/2^3 = 1V, and the minimum voltage change that can be distinguished is 1/2V. That is to say, when the input voltage is between 0-0. 5V, the output is actually 0, when from 0.5-1.5, the output is always 1, and so on. So the output is actually a step curve.

Combined with the aforementioned environmental noise, also known as thermal noise (thermal), then the total noise of an ADC is the square sum of thermal noise and quantization noise. Is it a bit of an upside to see here, this is actually just the beginning. For a given ADC, we have to quantify and measure its two noises, so that we can better and target the design of the entire system including the ADC.

Take the Delta-Sigma ADC as an example. These two types of noise depend on the resolution, reference voltage, and output rate of the ADC. For a system that includes an ADC, this noise analysis is more complicated. In a typical analog-to-digital conversion system, it usually contains various analog noise filters, operational amplifiers, ADCs, and digital filters, FPGAs, MCUs and other analog digital chips that process digital signals, which also constitute a signal chain. . To analyze the noise of this signal chain, we must not only do noise analysis on the ADC itself, but also examine the noise of each component in the entire signal chain and the mutual influence between all these components. This thing sounds complicated, but we can use the effective noise bandwidth of the signal chain (Effective Noise Bandwidth) to quantify this analysis process. Of course, we also need a series of tools, software and reference materials to help us do quantitative analysis.

In fact, much of the previous content comes from TI’s e-book “Basics of High-Accuracy ADC Noise Analysis.” This book combines the design and practical experience of a large number of TI engineers, and introduces in detail the noise sources of ADCs, how to quantify and analyze them, and how to effectively design circuits to optimize the noise performance of ADCs. This book is very easy to understand, and it also takes into account the depth of technology. It is highly recommended to everyone.

In the aforementioned TI “High Precision Laboratory” tutorial, in addition to the drive circuit design and noise analysis introduced here, there are also the most basic ADC foundation, the principle and comparison of SAR and Delta-sigma ADC, error analysis, Low-power design, high-speed design, etc., are very comprehensive. There are supporting exercises after each video to facilitate us to consolidate the learning results. I think whether you are a novice or a veteran of analog electronics, you can find content that suits you.

“High-precision laboratory” and ADC circuit design guide manual are part of TI ADC toolbox. There is also “Analog Engineer Pocket Reference Book”, which can be used to quickly find and calculate various signal chain tuning methods, including Op amp bandwidth, stability, etc. These design resources can be used in conjunction with ADC analog engineer calculator, TI TINA and Pspice for TI to form a one-stop design experience. I put the links to these contents in the reference materials below. Friends who want to learn this knowledge must remember to start here.

The Links:   TM121SV-02L07D EVM31-060 POWER-IGBT