“When designing a digital circuit system, whether the timing can meet the requirements directly affects the function and performance of the circuit. This paper first explains the important concepts in timing analysis, and links these concepts with the performance of digital systems. Finally, combined with the design of FPGA, it points out the content of timing constraints and the precautions in timing constraints.
When designing a digital circuit system, whether the timing can meet the requirements directly affects the function and performance of the circuit. This paper first explains the important concepts in timing analysis, and links these concepts with the performance of digital systems. Finally, combined with the design of FPGA, it points out the content of timing constraints and the precautions in timing constraints.
1. Important concepts in timing analysis
There are two very important concepts in digital systems: setup time and hold time, the schematic diagram of which is shown in Figure 1. Whether a digital system works or not is closely related to these two concepts. Only when both the setup time and the hold time are satisfied at the same time, the digital system can work reliably and normally.
When the setup time or hold time of the register cannot be met, the register may enter a metastable state. Metastable state is an intermediate state of voltage. Assuming that the output Voltage of the register is greater than 3V, it is judged as logic 1, and if it is less than 0.3V, it is judged as logic 0, then the state where the voltage is between 0.3V and 3V and can be stable for a short time is metastable. state. The register will return to the normal state after entering the metastable state for a period of time, but it may return to the state of logic 1, or it may return to the state of logic 0. This uncertainty can lead to errors in the digital system.
The setup time and hold time are inherent properties of a register, which are determined by its internal structure, process and other factors. Therefore, when designing a digital system, only by changing the circuit structure to meet the requirements of the setup time and hold time, and The setup time and hold time values cannot be changed.
2. The effect of setup time and hold time ON circuit performance
Let’s first look at a schematic diagram of a typical synchronous digital system, as shown in Figure 2.
In Figure 2, FF1 and FF2 represent two registers, between which there is combinatorial logic. The synchronous digital system is composed of many registers and the combinational logic among the registers (including the direct connection between the registers).
Obviously, the setup and hold times of each register must be met if the digital system is to work properly. Assuming that the clock signal ck arrives at all registers at the same time, Figure 3 shows the timing relationship between these two registers.
As can be seen from the figure, if the setup time and hold time of FF2 are to be satisfied, the following formulas must be satisfied:
Among them, Ts is the setup time, Th is the hold time, Tclock is the clock cycle, Tclk2q is the transmission delay of the register (the time from the valid edge of the clock to the output), and Tdelay is the combinational logic delay between the two registers.
It can be seen from equation (1) that whether the settling time can be satisfied depends on three parameters: clock period, register transfer delay and combinational logic delay. The output delay of the register is an inherent property of the register and cannot be changed. Therefore, in the design, the clock cycle and the delay of the combinational logic can only be adjusted to meet the requirements of the register for the establishment time.
It can be seen from formula (2) that whether the hold time can be satisfied depends on two parameters: the transmission delay of the register and the delay of the combinational logic. All the designer can do is to adjust the delay of the combinational logic.
Figure 3 is just the timing relationship between two registers. There are often thousands of registers in a digital system. The timing relationship between any two adjacent registers must satisfy formula (1) and formula ( 2), only in this way the digital system can work properly. Under the premise that the digital system can work normally, the delay of the combinational logic determines the upper limit of the clock frequency that the digital system can work with. The shorter the delay of the combinational logic, the higher the upper limit of the operating frequency of the system. The delay of the combinational logic here refers to the longest combinational logic delay between any two adjacent registers, that is, the critical path. delay. Of course, the delay of combinational logic cannot be infinitely short, and must meet the requirements of formula (2).
3. Constrain the timing in FPGA
In FPGA design, timing constraints play an important role. Timing constraints have two main functions: first, the EDA tool will try to place and route according to the designer’s constraints, and try to meet the timing requirements proposed by the designer; second, the EDA tool cannot meet the designer’s requirements after efforts. A warning message will be given to remind the designer when the timing requirements are met.
Be just right when constraining the design, too loose or too tight constraints will not make the circuit optimal. It goes without saying that the constraints are too loose. After the constraints are too tight, the EDA software still cannot meet the requirements after trying hard, but it will not take the one closest to the target, but will use the last one as the result, which may lead to worse circuit performance.
There are mainly three kinds of timing constraints in today’s FPGA design: one is the constraint from register to register, the other is constraint from pin to register, and the third is constraint from register to pin.
The register-to-register constraint is a constraint on the clock cycle, which corresponds to Tclk2q+Tdelay+Ts in formula (1). Generally speaking, the designer should have some idea of how fast the clock frequency needs to be in the system he designed. The constraints on the clock cycle need to be given.
When constraining the clock period, what is actually guaranteed is the register at the next level of the two registers. The first-level register is connected to the external pin of the FPGA, so whether the first-level register can meet the constraints of its establishment time and hold time depends on the relationship between the clock and data on the pin and the delay of each reaching the register. Assuming that the pin clock and the internal clock are synchronized (both in frequency and phase), the timing relationship between the data pin and the clock pin and the delay from the pin to the input of the register together determine the setup time of the first register and Whether the hold time can be met, the designer can constrain the delay from the data pin to the input of the register.
In order to ensure that the timing relationship between the output signal and the clock of the FPGA achieves the expected effect, for example, to meet the requirements of the next-level chip for the timing relationship between the clock and the data, the designer can restrict the delay experienced from the output of the register to the pin.
The above three constraints can cover all registers in the design. But in some specific cases, such as asynchronous clock domains, we clearly know that some registers will have a setup time or hold time that is not satisfied, but this is unavoidable, and the designer has also dealt with it . In this case, the designer is better off telling the EDA software to ignore these paths, otherwise the EDA software will make an effort to resolve timing conflicts on these paths, which is time consuming and ineffective.