Arteris IP launches Harmony Trace™️ Design Data Intelligence solution to help realize automatic traceability of system-on-chip semiconductor designs

Arteris IP, an industry-leading system-ON-chip (SoC) system IP provider that provides network-on-chip (NoC) interconnection IP and IP deployment technology to accelerate SoC creation, recently announced the launch of Arteris® Harmony Trace™️ Design Data Intelligence solution to simplify compliance with semiconductor industry functional safety and quality standards such as ISO 26262, IEC 61508, ISO 9001 and IATF 16949.

Arteris IP launches Harmony Trace™️ Design Data Intelligence solution to help realize automatic traceability of system-on-chip semiconductor designs

Highlights of this release:

● Harmony Trace improves system quality and accelerates functional safety assessment by identifying and fixing traceability gaps between different systems.

● Harmony Trace is executed as a server-based enterprise-level application with a web-based user interface (UI).

● Harmony Trace is unique because it allows engineers to freely use the “best tool for the job” and automatically link requirements and artifacts.

For design teams with functional safety requirements or creating complex SoCs or systems, Arteris® Harmony Trace™️ can improve system quality and the ability to achieve functional safety certification. By creating and maintaining the traceability of requirements, specifications, EDA and hardware design, software code, and documentation between different systems, engineers will immediately know when a change has occurred and the impact of the change on other design artifacts and system components .

Harmony Trace is implemented as a server-based enterprise-level application. It has a web-based user interface that can interface with EDA, documentation, existing requirements, software engineering, and support systems. Different from solutions such as application lifecycle management (ALM) and product lifecycle management (PLM), this type of solution requires engineers to use a single environment that is not optimal in any respect, and Arteris Harmony Trace creates one based on all systems The system makes the entire SoC design process and product life cycle demand tracking completely visible.

“Developing a complex SoC often involves a series of different and unrelated tools, which makes it difficult to maintain a record to track design requirements and artifacts during the product life cycle,” said Mike Demler, senior analyst at the Linley Group . “But Arteris Harmony Trace alleviates these problems by connecting different tools in isolation so that users can track requirements, implementation, verification, and document mismatches in existing systems. This means that engineers can continue to use first-class solutions and technologies, such as EDA tools, IBM DOORS, Jama, Jira, DITA and IP-XACT, while experiencing the benefits of automatic traceability. Harmony Trace helps design teams meet the quality and change management requirements of functional safety standards such as ISO 26262 and IEC 61508.”

“The development of Arteris Harmony Trace is driven by the needs of our customers. Customers need to establish an automatic traceability process between their existing requirements, specifications, EDA, code base and documentation tools, and implement best practices for change management. “Said K. Charles Janac, President and CEO of Arteris IP. “Due to its unique Semiconductor industry-specific semantic computing technology, Harmony Trace enables our customers to use their existing tools and automatically link data between them.”